test_harness_system_bd: Fix axi_cpu_interconnect bug for MI >= 16 #47
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I believe that this issue would be better addressed if the axi_cpu_interconnect implemented as a SmartConnect instance is configured to use only AXI4LITE interfaces. This is because mng_axi_vip which connects to the axi_cpu_interconnect as a master interface only uses AXI4LITE read/write transfers. The SmartConnect 16 MI limitation which is encountered during the current simulation run can be relaxed to 64 MI AXI4LITE according to the documentation:
However, this will have to be further investigated, since after some experiments in which I set all MIs to AXI4LITE, an error is received: So, in the meantime, until this issue is solved. I suggest fetching the latest changes on the main branch and using AXI Interconnects through the following setting: |
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Closing this PR as another PR has been opened to solve the issue of cascading interconnects. |
In test_harness block design, axi_mem_interconnect is connected to axi_cpu_interconnect but in case axi_cpu_interconnect has more than 16 interfaces connected, a smartconnect error will occur: "ERROR: [xilinx.com:ip:smartconnect:1.0-1] test_harness_axi_cpu_interconnect_0: For SmartConnect test_harness_axi_cpu_interconnect_0, the use of >16 MI is reserved for low-bandwidth pathways only. Either the SI must be AXI4LITE or all MI must be 32-bit-wide AXI4LITE. Otherwise, you may cascade multiple instances with <=16 MI".
So in order to solve this another smartconnect is used to separate the axi_mem_interconnect from the axi_cpu_interconnect!
This was tested only for the adrv9009 Testbench!